Overview

Problems 1-11.5

Complete problems covering topics from Chapter 2 and 3 (use either document format; Clearly show work; Typed work is preferred):

Problem 11.6: State Machine in JLS

Problem 11 is described in the document/pdf and is an extension of an example problem from chapter 3, however you need to complete an implementation for it in JLS.

  1. You must create a digital logic circuit from basic parts that we’ve covered (any basic gates, or multiplexors, decoders, and flip-flops). You CAN NOT use the JLS state machine tool, the memory block, or the truth table component.
  2. You should use the rising edge of the clock to trigger state changes. (Flip-flops)
  3. You can assume the clock is “5 seconds of time”. For simulation purposes, assume that’s 100 units of simulation time.
  4. If you’d like to use an online tool to help you draw the state machine, former CSE 132 Head TA Emily Wilson has an updated Finite State Machine Designer online App: https://wilsonem.github.io/fsm/
  5. Download and work in this JLS starter: hw3a_11p6.jls
    • DO NOT change the names of either input or output ports. The Autograder depends on them being named as-is.

Submission

You will need to submit your assignment via Gradescope. Part of the submission process will require you to indicate where your work is for each individual problem. Please:

There are two distinct Gradescope assignments listed: one for all written questions and one for the JLS circuit.

JLS problems are unit tested for the grade. When you submit to Gradescope the test cases will be run and results should be available within a few minutes. You can stay on the submission page to see the resutls or come back to it later. Usually you can review details of each passed or failed test case and, if needed, try to recreate it in JLS for additional testing. You can review the results to try to fix any errors and resubmit.