Setup

Create a Repo

1. Navigate to link
2. If shown a list of IDs, select your WUSTL Key from the list (this only needs to be done once. If you already did this during studio, you won’t be given the optiona gain)
   
3. “Accept the assignment”.
   
4. Follow the link to the new repository for the group:
   

Codespaces

1. We’ll be using Codespaces for many studios and assignments.
2. Create a code space from the repository:
   

Problem 1: Your assignment: Simple Combinational Logic

1. Run the 1.1 simple_comb testbench verification task (Click the VSCode Tasks icon on the side bar () and then the task’s name). Observe that the PROBLEMS tab shows that several test cases failed:

   

2. The “Surfer” pane will allow you to explore signals that were being used in the text. Expand the simple_comb_tb (this is the test bench), then the dut (the “device under test”), then select variables a, b, and c:

   

3. Notice the picture above only shows the initial values of a, b, and c, but you should be able to see the full signal (zoom in/out or scroll). If you click the mouse along the signal it will show you the values of each at exaclty that instant. Or if you click and drag you can see how they change as time changes. Review them from the beginning (t=0) to the end (t=170).

4. Run the 0.0 Edit questions.md task and answer question 1 in the designated place (don’t remove the # Q lines!, but remove/replace the TODO lines. You can answer with plain text, although you are also welcome to use MarkDown notation for styling if you’d like).

5. Run the 1.2 Edit simple_comb.sv task. Review the desciption of what’s expected and fix the designated line using basic Verilog operations (behavioral Verilog with symbols for the operations, like & for AND).

6. Re-run 1.1 simple_comb testbench verification and confirm that all tests pass in the PROBLEMS pane. (Or, if not, continue to edit simple_comb.sv).

7. Once it correctly passes the test bench, run ask 1.3 Simulate simple_comb.sv, which will allow you to simulate the circuit. Be sure to hit the “play” button in the DIGITALJS: CONTROL pane to simulate the circuit.

8. Set c to a 1 and both a and b to 0.

9. Complete Q2 in questions.md.

10. The “synthesizer” takes our HDL description and breaks it down into simpler parts. Run task 1.4 AIG Mapping. Complete Q3 and Q4 in questions.md.

Problem 2: Verilog Structure

Consider the circuit:

1. Use task 2.1 Edit structural.sv and complete the HDL description using structural modeling!

   Primitive gates can be modeled with the format: type(output, inputs...). For example, a 3-input or gate could be modeled with or(output, a, b, c); or with a unique name for the instance of the or gate, like or gate1(out, a, b, c);.

   Caution!

   The problem asks for a structural model. You should not use assign or always_comb statements. You should use the primitive parts and(...), or(...), not(...), etc. Although you may pass test cases with other forms of modeling, credit will only be given for a structural model.

2. Use the 2.2 Simulate structural.sv task and the 2.5 structural testbench tasks to test your work. Revise your work until you pass the testbench (but, again, be sure you are using ONLY structural elements. No use of operators like ~, ^, &, etc.)

3. Run task 2.4 (AIG Mapping) and 2.5 (iCE40 Mapping) and answer Q5 in questions.md.

Problem 3: Basic addition - Revisiting Hw 2a

Consider adding 2-digit binary numbers, $a$ and $b$ to produce the 2-bit result, $s$ and a one-bit carry-out, $c$:

1. Use task 3.1 to edit add2.sv. Complete it as described. Use tasks 3.2 and 3.3 to test your work. Update it until you pass all tests.

2. Complete Q7-Q10 in questions.md

End of work

Submission

The assignment will be submitted via GitHub and Gradescope.

1. First, be sure to commit and push files to GitHub (as shown in studio).

1.1

1.2

1.3

2. Then go to GitHub.com and confirm the updates are on GitHub

3. Finally (after confirming updates are on GitHub), go to the assignment in Gradescope and import it from GitHub:

3.1

3.2

• Submission Link: Gradescope